Improved Floating-Point Matrix Multiplier

* This work is partially supported by NSC 99-2221-E-260-010-. † Correspondence to: D.-R. Duh; E-mail address: [email protected] Abstract – Floating-point matrix multiplier is widely used in scientific computations. A great deal of efforts has been made to achieve higher performance. The matrix multiplication consists of many multiplications and accumulations. Yang and Duh proposed a modular design of floating-point matrix multiplier which reserving intermediate result as two vectors. It brings shorter delay but more cost. This work modifies Yang and Duh’s design with Booth encoding in multiplication to reduce the number of partial products. As the result, the improved floating-point matrix multiplier has better performance with shorter delay and much less hardware cost than Yang and Duh’s design.